Self-aligned contact for silicon-on-insulator devices

ABSTRACT

A method for forming a self-aligned contact to an ultra-thin body transistor first providing an ultra-thin body transistor with source and drain regions operated by a gate stack; forming a contact spacer on the gate stack; forming a passivation layer overlying the transistor; forming a contact hole in the passivation layer exposing the contact spacer and the source/drain regions; filling the contact hole with an electrically conductive material; and establishing electrical communication with the source/drain region.

FIELD OF THE INVENTION

The present invention generally relates to the field of semiconductordevices and more particularly, to the manufacture of advanced metaloxide semiconductor field effect transistors (MOSFETs) with self-alignedcontacts.

BACKGROUND OF THE INVENTION

Transistor scaling has provided continued improvement in speedperformance and circuit density in ultra-large scale integrated (ULSI)chips over the past few decades. As the gate length of the conventionalbulk metal-oxide-semiconductor field-effect transistor (MOSFET) isreduced, it suffers from problems related to the inability of the gateto substantially control the on and off states of the channel. Phenomenasuch as reduced gate control associated with transistors with shortchannel lengths are termed short-channel effects. Increased body dopingconcentration, reduced gate oxide thickness, and ultra-shallowsource/drain junctions are ways to suppress short-channel effects.However, for device scaling well into the sub-30 nm regime, therequirements for body doping concentration, gate oxide thickness, andsource/drain (S/D) doping profiles become increasingly difficult to meetin conventional device structures where bulk silicon substrates areemployed.

A promising approach to control short-channel effects and to sustain thehistorical pace of scaling is to use alternative device structures suchas ultra-thin body transistors and multiple-gate transistors. Anultra-thin body (UTB) transistor has a body thickness that is less thanhalf the gate length. In an ultra-thin body transistor, all currentpaths between the source and drain are in close proximity to the gate,resulting in good gate control of the channel potential. Multiple-gatetransistor structures include the double-gate structure, triple-gatestructure, omega-FET structure, and the surround-gate or wrap-aroundgate structure. A multiple-gate transistor structure is expected toextend the scalability of CMOS technology beyond the limitations of theconventional bulk MOSFET and realize the ultimate potential of siliconMOSFETs. The introduction of additional gates improves the capacitancecoupling between the gates and the channel, increases the control of thechannel potential by the gate, helps to suppress short channel effects,and prolongs the scalability of the MOS transistor.

In the above-mentioned nanoscale device structures (including UTBtransistors and multiple-gate transistors), the high current densityflowing in the devices means that series resistances are an importantconsideration in the optimization of device performance. In addition,variations in the series resistance in the source and drain regions ofthe device result in significant variations in the electricalcharacteristics of the device. A manufacturable process needs to have anadequate robustness to ensure that variations in the device seriesresistance are kept to a minimum.

For illustration purposes, an advanced device structure such as anultra-thin body (UTB) transistor is first considered. FIG. 1A shows anenlarged, plane view of the UTB transistor 10. FIG. 1B shows anenlarged, cross-sectional view through the dashed line A-A′ of FIG. 1A.The UTB transistor 10 comprises an ultra-thin body 12 overlying aninsulator layer 14 and a silicon substrate 30. A transistor with asource 16 and a drain 18 separated by a gate electrode 20 is formed onthe ultra-thin body 12. The gate electrode 20 is further insulated by aspacer 32 and a gate dielectric layer 34. A silicide layer 22 is formedin the source and drain regions 16,18. Electrical connections to thesource and drain regions 16,18 are formed by conductive contacts 24,26to the silicided contact area 22. Electrical current flowing from thesource contact 24 to the drain contact 26 passes from source contact 24into the silicided contact area 22 in the source, enters the sourceregion 16, the channel region 28 of the transistor 10, and into thedrain region 18. The current then flows from the drain region 18 to thesilicided contact area 22 in the drain region 18 to the drain contact26. The current encounters resistances in various parts of thetransistor 10 as mentioned above. In an actual manufacturing process,the conductive contacts 24,26 may be misaligned.

Referring now to FIG. 2, an example of a misaligned contact isillustrated. In this example, both the source and the drain contacts24,26 are misaligned to the right. Consequently, the distance betweenthe source contact 24 and the channel region 28 is reduced, while thedistance between the drain contact 26 and the channel region 28 isincreased. This results in a reduced source resistance and an increaseddrain resistance. Such variations in the source and drain resistances inthe transistor 40 results in variations in the device characteristics.

It is therefore an object of the present invention to provide aself-aligned contact hole for nanoscale silicon-on-insulator (SOI)devices.

It is another object of the present invention to provide a method forforming nanoscale SOI devices with self-aligned source and draincontacts.

SUMMARY OF THE INVENTION

In accordance with the present invention, a method for forming aself-aligned contact to an ultra-thin body transistor and the contactthus formed are disclosed.

In a preferred embodiment, a method for forming a self-aligned contactto an ultra-thin body transistor can be carried out by the operatingsteps of providing an ultra-thin body transistor including a sourceregion and a drain region separated by a gate stack; forming a contactspacer on the gate stack; forming a passivation layer overlying theultra-thin body transistor; forming a contact hole in the passivationlayer exposing the contact spacer and the source/drain region; andfilling the contact hole with an electrically conductive material forestablishing electrical communication with the source/drain region.

In the method for forming a self-aligned contact to an ultra-thin bodytransistor, the gate stack may be a gate electrode which may be formedof a material of poly-crystalline silicon or poly-crystallinesilicon-germanium. The gate electrode may be formed of a refractorymetal. The gate stack may include a gate electrode and a gate cappinglayer, wherein the gate capping layer may be a dielectric material, orsilicon nitride. The gate capping layer may further be a silicon nitridelayer overlying a silicon oxide layer.

The contact spacer may be a dielectric material, may be a siliconnitride, or may be a composite spacer. The contact spacer may have awidth between about 20 angstroms and about 5000 angstroms. Thepassivation layer may be formed of a dielectric material, may be formedof silicon oxide, or may be formed to a thickness between about 500angstroms and about 3000 angstroms. The electrically conductive materialmay be a metal, or may be a nitride of titanium nitride or tantalumnitride.

The present invention is further directed to a method for forming aself-aligned contact to a multiple-gate transistor which may be carriedout by the operating steps of providing a multiple-gate transistor thatincludes a source region and a drain region separated by a gate stack;forming a contact spacer on the gate stack; forming a passivation layeroverlying the multiple-gate transistor; forming a contact hole in thepassivation layer exposing the contact spacer and the source/drainregion; and filling the contact hole with an electrically conductivematerial for establishing electrical communication with the source/drainregion.

The method for forming a self-aligned contact to a multiple-gatetransistor may further include the step of providing the multiple-gatetransistor in a double-gate transistor, in a triple-gate transistor, orin an omega field-effect transistor. The gate stack may be a gateelectrode which may be formed by a material selected of poly-crystallinesilicon or poly-crystalline silicon-germanium. The gate electrode mayinclude a gate material such as a refractory metal. The gate stack mayinclude a gate electrode and a gate capping layer, wherein the gatecapping layer may be formed of a dielectric material, may be formed ofsilicon nitride, or may be formed of silicon nitride layer overlying asilicon oxide layer.

In the method for forming a self-aligned contact to a multiple-gatetransistor, the contact spacer may be formed of a dielectric material,may be formed of silicon nitride, or may be formed of a compositematerial. The contact spacer may have a width between about 20 angstromsand about 5000 angstroms. The passivation layer may be a dielectricmaterial, may be silicon oxide, or may have a thickness between about500 angstroms and about 3000 angstroms. The electrically conductivematerial may be tungsten or may be a nitride of titanium nitride andtantalum nitride.

The present invention is further directed to a self-aligned contactdevice which includes an ultra-thin body transistor including a sourceregion and a drain region separated by a gate stack; a contact spacerformed on the side of the gate stack; and an electrically conductivecontact in contact with the contact spacer and in electricalcommunication with the source/drain region.

The self-aligned contact device may be a gate electrode, which may beformed of a material of poly-crystalline silicon or poly-crystallinesilicon-germanium. The gate electrode may include a gate material of arefractory metal. The gate stack may include a gate electrode and a gatecapping layer, wherein the gate capping layer may be a dielectric,silicon nitride, or a silicon nitride layer overlying a silicon oxidelayer. The contact spacer may be a dielectric, silicon nitride, or acomposite spacer. The contact spacer may be formed to a width betweenabout 20 angstroms and about 5000 angstroms. The passivation layer maybe formed of a dielectric or may be formed of silicon oxide. Thepassivation layer may be formed to a thickness between about 500angstroms and about 3000 angstroms. The electrically conductive materialmay be tungsten or may be a nitride of titanium nitride or tantalumnitride.

The present invention is still further directed to a self-alignedcontact device which includes a multiple-gate transistor that includes asource and a drain separated by a gate stack; a contact spacer formed onthe side of the gate stack; and a conductive contact in contact with thecontact spacer and in electrical communication with the source anddrain.

In the self-aligned contact device, the multiple-gate transistor may bea double-gate transistor, a triple-gate transistor, or an omegafield-effect transistor. The gate stack may be a gate electrode, whichmay be formed of poly-crystalline silicon or poly-crystallinesilicon-germanium. The gate electrode may be formed of a refractorymetal. The gate stack may include a gate electrode and a gate cappinglayer which may be formed of a dielectric, of a silicon nitride, or of asilicon nitride layer overlying a silicon oxide layer. The contactspacer may be a dielectric, may be silicon nitride, or may be acomposite spacer. The contact spacer may have a width between about 20angstroms and about 5000 angstroms. The passivation layer may be formedof a dielectric material or may be formed of a silicon oxide. Thepassivation layer may be formed to a thickness between about 500angstroms and about 3000 angstroms. The electrically conductive materialmay be tungsten or may be a nitride of titanium nitride or tantalumnitride.

BRIEF DESCRIPTION OF THE DRAWINGS

These and other objects, features and advantages of the presentinvention will become apparent from the following detailed descriptionand the appended drawings in which:

FIGS. 1A and 1B are an enlarged, plane view and an enlarged,cross-sectional view, respectively, of a conventional ultra-thin bodytransistor.

FIG. 2 is an enlarged, cross-sectional view of a conventional ultra-thinbody transistor with a misaligned contact.

FIGS. 3A and 3B are an enlarged, plane view and an enlarged,cross-sectional view, respectively, of a present invention ultra-thinbody transistor with self-aligned contact.

FIGS. 4A and 4B are enlarged, cross-sectional views of a presentinvention ultra-thin body transistor with and without a self-alignedcontact, respectively.

FIGS. 5A-5C are enlarged, cross-sectional views illustrating theformation process of the present invention self-aligned contact to anultra-thin body transistor.

FIGS. 6A-6C are enlarged, plane views illustrating the formation of thepresent invention self-aligned contact to an ultra-thin body transistor.

FIG. 7 is an enlarged, perspective view of a present inventiontriple-gate transistor prior to the formation of the self-alignedcontact.

FIG. 8 is an enlarged, cross-sectional view taken along line C-C′ ofFIG. 7 through the gate electrode.

FIGS. 9A-9D are enlarged, cross-sectional views taken along line D-D′illustrating the process steps for forming the present inventionself-aligned contact to a triple-gate transistor.

FIGS. 10A-10D are enlarged, cross-sectional views taken along line E-E′illustrating the process steps for forming a self-aligned contact in atriple-gate transistor.

FIG. 11 is an enlarged, perspective view of an omega-FET.

FIG. 12 is an enlarged, perspective view of a double-gate transistor.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

The present invention concerns the provision of self-aligned contacts tothe source and drain regions in advanced semiconductor device structuressuch as ultra-thin body transistors, double-gate transistors such as thefinFET transistor, triple-gate transistors, and omega-FET. Transistorswith two or more gates, including the double-gate transistor, thetriple-gate transistor, and the omega-FET are termed “multiple-gatetransistors”.

In FIG. 3A, the plane view of an improved contact scheme for the UTBtransistor 50 is shown. An enlarged, cross-sectional view through thedash line B-B′ of FIG. 3A is shown in FIG. 3B. The contacts 24,26overlap a contact spacer 36, so that any slight misalignment in thesource and drain contacts 24,26 will not affect the distance between thesource contact 24 and the channel region 28 and the distance between thedrain contact 26 and the channel region 28. The distances between thesource contact 24 or the drain contact 26 and the channel region 28 isthe same as long as the contact holes 44,46 overlap the contact spacer36. The distance between the source contact 24 and the channel region 28is labeled X_(s), and the distance between the drain contact and thechannel region is labeled X_(d), as shown in FIG. 3D. FIG. 3B also showsthe definition of the width X_(c) of the contact spacer 36.

FIGS. 4A and 4B show transistor 60 in another embodiment of thisinvention. In FIGS. 4A and 4B, a gate capping layer 42 overlies the gateelectrode 20. In this embodiment, the tolerance for the contactmisalignment is larger. The provision of a mask, i.e. the gate cappinglayer 42, over the gate electrode 20 ensures that even if the contacts24,26 are grossly misaligned so that one of them overlaps the gateelectrode 20, an electrical short between the contacts 24,26 and thegate electrode 20 would not occur.

A method for the fabrication of the present invention UTB transistorwith self-aligned contact is now described. Referring now to FIGS. 5Aand 6A, a UTB transistor 70 is first formed. At this stage, the UTBtransistor 70 comprises a source 16 and a drain 18 separated by a gatestack 72. The gate stack 72 comprises a gate electrode 20. The gateelectrode 20 is formed of a gate material. The gate material may bepolycrystalline-silicon (poly-Si), poly-crystalline silicon-germanium(poly-SiGe), a refractory metal such as molybdenum and tungsten,compounds such as titanium nitride, or other suitable conductingmaterial. In the preferred embodiment, a gate capping layer 42 isprovided on the gate electrode 20. The gate stack 72 therefore comprisesthe gate capping layer 42 and the gate electrode 20, as shown in anenlarged, plane view of FIG. 6A. The gate capping layer 42 may be formedof a dielectric material such as silicon oxide, silicon nitride, or anyother suitable material that is insulating in nature. The gate cappinglayer 42 may also be formed of a silicon nitride layer overlying asilicon oxide layer.

Shown in FIGS. 5B and 6B, a contact spacer 36 is next formed. Thecontact spacer 36 is formed on the first spacer 32 of the device usingtechniques known and used in the art, i.e. deposition of the spacermaterial and anisotropic plasma etching. The contact spacer material maybe a dielectric material such as silicon nitride or silicon dioxide. Inthe preferred embodiment, the spacer is formed of silicon nitride. Thecontact spacer 36 may also be a composite spacer comprising a pluralityof layers such as a silicon nitride layer overlying a silicon oxidelayer. The width X_(c) of the contact spacer 36, shown in FIG. 3B, is inthe range between about 20 angstroms to about 5000 angstroms. Next, asshown in FIGS. 5C and 6C, a passivation layer 74 is deposited. Thepassivation layer 74 may be formed of a dielectric such as siliconoxide. For example, silicon oxide can be deposited by low pressurechemical vapor deposition using tetraethosiloxane (TEOS) as a precursorin a temperature range between about 650 degrees Celsius and about 900degrees Celsius. The thickness of the passivation layer 74 is betweenabout 500 angstroms and about 300 angstroms. Selected portions of thepassivation layer 74 are etched to form contact holes 44,46 in thepassivation layer. Etching may be accomplished in a reactive plasmaetcher using a reactant gas mixture such as carbon tetrafluoride andhydrogen. Contact holes 44,46 may overlap the contact spacers 36, asshown in the enlarged, plane view of FIG. 6C. Contact holes 44,46 arethen filled with an electrically conductive material. The electricallyconductive material may be a metal such as tungsten, a metallic nitridesuch as titanium nitride and tantalum nitride, or any other electricallyconducting materials. The contact holes 44,46 may also be filled with acombination of the above mentioned materials.

In the above illustration, a self-aligned contact scheme was describedfor an ultra-thin body transistor 70. The use of a contact spacer 36 forthe self-aligned contacts 24,26 may be applied in other advancedtransistor structures such as double-gate transistors, triple-gatetransistors, and omega-FETs.

Referring now to FIG. 7, a triple-gate transistor 80 is shown. Thetriple-gate transistor 80 of FIG. 7 is completed up to the process stepprior to contact formation. The triple-gate transistor 80 has a source16 and drain 18 separated by a gate stack 72. The source/drain regions16,18 may be formed of a silicide (not shown) and a heavily-dopedsource/drain (similar to the ultra-thin body transistor). FIG. 8 showsan enlarged, cross-section view of the triple-gate transistor 80 of FIG.7 in the line containing C-C′. The line containing C-C′ of FIG. 7 cutsthrough all three gates 82,84,86 of the gate electrode 20 as well as thechannel region 28. Referring to FIG. 8, a gate dielectric layer 34 wrapsaround the silicon fin 90 in the channel region 28 of the triple-gatetransistor 80. The gate electrode 20 in the triple-gate transistor 80straddles over the silicon fin 90. The gate electrode 20 forms threegates: one gate 84 on the top surface 88 of the silicon fin 90, and twogates 82,86 on the sidewalls 92,94 of the silicon fin 90.

An enlarged, cross-sectional view taken along line D-D′ of FIG. 7 isshown in FIG. 9A. This cross-section cuts through the fin 90 and the topgate 84. The cross-section in the line containing E-E′ of FIG. 7 isshown in FIG. 10A. This cross-section cuts through the fin 90 and thetwo gates 82,86 on the sidewalls 92,94 of the fin 90. It should be notedthat the gate electrode 20 may comprise a gate capping layer 42overlying an electrically conductive gate material. The gate materialmay be comprised of poly-Si, poly-SiGe, a refractory metal such asmolybdenum and tungsten, compounds such as titanium nitride, or otherconducting materials.

A simple process flow for fabricating the self-aligned contact for atriple-gate structure is to be described. FIGS. 9A-9D and 10A-10Dillustrate the process for forming the self-aligned contacts 24,26. Themethod for forming a self-aligned contact begins with the completedtriple-gate transistor 80 as shown in FIGS. 9A and 10A. A contact spacer36 is formed, as shown in FIGS. 9B and 10B. The contact spacer 36 isformed using techniques known in the art for spacer formation, i.e.deposition of the spacer material and anisotropic plasma etching. Thecontact spacer material may be a dielectric material such as siliconnitride and silicon dioxide. In the preferred embodiment, the spacermaterial is a silicon nitride. The contact spacer 36 may also be acomposite spacer formed by a plurality of layers such as a siliconnitride layer overlying a silicon oxide layer. The width of the contactspacer 36, shown in FIGS. 9B and 10B, is in the range from about 20angstroms to about 5000 angstroms. This is followed by the deposition ofa passivation layer 74. The passivation layer 74 may be formed of adielectric such as silicon oxide. For example, silicon oxide can bedeposited by low pressure chemical vapor deposition usingtetraethosiloxane (TEOS) as a precursor at a temperature between about650 degrees Celsius and about 900 degrees Celsius. The thickness of thepassivation layer 74 is preferably in the range from about 500 angstromsto about 3000 angstroms. Selected portions of the passivation layer 74are patterned using lithography techniques and etched to form contactholes 44,46. Etching may be accomplished in a reactive plasma etcherusing a reactant gas mixture such as carbon tetrafluoride and hydrogen.Contact holes 44,46 may overlap the contact spacers 36, as shown inFIGS. 9C and 10C. Contact holes 44,46 are then filled with anelectrically conductive material, as shown in FIGS. 9D and 10D. Theconductive contact material may be a metal such as tungsten, a metallicnitride such as titanium nitride and tantalum nitride, or any otherconducting material. The contact hole may also be filled with acombination of the above mentioned materials.

The self-aligned contact formation process may also be applied to otheradvanced device structures. For example, the omega-FET structure 100shown in FIG. 11, and the double-gate transistor structure 110 shown inFIG. 12, is similar to the triple-gate transistor structure 80. Theself-aligned contact process described for the triple-gate transistor 80may be applied generally to other multiple-gate transistors, such as thedouble-gate transistor 110 or the omega-FET 100.

While the present invention has been described in an illustrativemanner, it should be understood that the terminology used is intended tobe in a nature of words of description rather than of limitation.

Furthermore, while the present invention has been described in terms ofa preferred and alternate embodiment, it is to be appreciated that thoseskilled in the art will readily apply these teachings to other possiblevariations of the inventions.

The embodiment of the invention in which an exclusive property orprivilege is claimed are defined as follows.

1. A method for forming a self-aligned contact to an ultra-thin bodytransistor comprising the steps of: providing an ultra-thin bodytransistor comprising a source region and a drain region separated by agate stack; forming a contact spacer on said gate stack; forming apassivation layer overlying said ultra-thin body transistor; forming acontact hole in said passivation layer exposing said contact spacer andsaid source/drain region; and filling said contact hole with anelectrically conductive material for establishing electricalcommunication with said source/drain region.
 2. The method of claim 1,wherein said gate stack comprises a gate electrode.
 3. The method ofclaim 2, wherein said gate electrode is formed of a material selectedfrom the group consisting of poly-crystalline silicon andpoly-crystalline silicon-germanium.
 4. The method of claim 2, whereinsaid gate electrode comprises a gate material of a refractory metal. 5.The method of claim 1, wherein said gate stack comprises a gateelectrode and a gate capping layer.
 6. The method of claim 5, whereinsaid gate capping layer comprises a dielectric.
 7. The method of claim5, wherein said gate capping layer comprises a silicon nitride.
 8. Themethod of claim 5, wherein said gate capping layer comprises a siliconnitride layer overlying a silicon oxide layer.
 9. The method of claim 1,wherein said contact spacer comprises a dielectric.
 10. The method ofclaim 1, wherein said contact spacer comprises silicon nitride.
 11. Themethod of claim 1, wherein said contact spacer is a composite spacer.12. The method of claim 1, wherein said contact spacer has a widthbetween about 20 angstroms and about 5000 angstroms.
 13. The method ofclaim 1, wherein said passivation layer comprises a dielectric.
 14. Themethod of claim 1, wherein said passivation layer comprises siliconoxide.
 15. The method of claim 1, wherein said passivation layer has athickness in the range between about 500 angstroms and about 3000angstroms.
 16. The method of claim 1, wherein said electricallyconductive material is a metal.
 17. The method of claim 1, wherein saidelectrically conductive material is a nitride selected from the groupconsisting of titanium nitride and tantalum nitride. 18-37. (canceled)38. A self-aligned contact device comprising: an ultra-thin bodytransistor comprising a source region and a drain region separated by agate stack; a contact spacer formed on the side of the gate stack; andan electrically conductive contact in contact with said contact spacerand in electrical communication with said source/drain region.
 39. Thedevice of claim 38, wherein said gate stack comprises a gate electrode.40. The device of claim 39, wherein said gate electrode comprises a gatematerial selected from the group consisting of poly-crystalline siliconand poly-crystalline silicon-germanium.
 41. The device of claim 39,wherein said gate electrode comprises a gate material of a refractorymetal.
 42. The device of claim 38, wherein said gate stack comprises agate electrode and a gate capping layer.
 43. The device of claim 42,wherein said gate capping layer comprises a dielectric.
 44. The deviceof claim 42, wherein said gate capping layer comprises silicon nitride.45. The device of claim 42, wherein said gate capping layer comprises asilicon nitride layer overlying a silicon oxide layer.
 46. The device ofclaim 38, wherein said contact spacer comprises a dielectric.
 47. Thedevice of claim 38, wherein said contact spacer comprises siliconnitride.
 48. The device of claim 38, wherein said contact spacer is acomposite spacer.
 49. The device of claim 38, wherein said contactspacer has a width between about 20 angstroms and about 5000 angstroms.50-52. (canceled)
 53. The device of claim 38, wherein said electricallyconductive contact is formed of tungsten.
 54. The device of claim 38,wherein said electrically conductive contact is formed of a nitrideselected from the group consisting of titanium nitride and tantalumnitride. 55-74. (canceled)